Establishing millions of connections on a silicon wafer the size of one square millimeter.

From nanometers to angstroms, chip manufacturers are doing their utmost to shrink the size of circuits. However, for the ever-growing computational power needs of people, a technology involving larger sizes (hundreds or thousands of nanometers) may be equally important in the next five years.

This technology is called Direct Hybrid Bonding, which can stack two or more chips together in the same package to build the so-called 3D chips. Despite the gradual collapse of Moore's Law, the rate of transistor miniaturization is slowing down, but chip manufacturers can still increase the number of transistors in processors and memory in other ways.

In May of this year, at the IEEE Electronic Components and Technology Conference (ECTC) held in Denver, research teams from around the world announced various hard-won improvements to this technology, some of which showed that the connection density between 3D stacked chips may reach a record level: about 7 million connections per square millimeter of silicon wafer.

Yi Shi from Intel reported at the ECTC conference that all these connections are necessary due to new advances in semiconductor technology. Moore's Law is now dominated by a concept called System Technology Co-Optimization (STCO), which means that the functions of the chip (such as cache, input/output, and logic) are manufactured separately using the most advanced process technology. These subsystems can then be assembled using hybrid bonding and other advanced packaging technologies to make them work like a single silicon wafer. But this can only be achieved when there are high-density connections that can transmit data between separate silicon wafers with almost no delay or energy consumption.

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Among all advanced packaging technologies, hybrid bonding provides the highest density of vertical connections. Therefore, it is the fastest-growing field in the advanced packaging industry. Gabriella Pereira, a technology and market analyst at Yole Group, said that by 2029, the market size in this direction will triple, reaching 38 billion US dollars. It is expected that by then, hybrid bonding will account for about half of the market.

In hybrid bonding, copper pads are established on the top surface of each chip. Copper is surrounded by an insulating layer (usually silicon dioxide), and the pad itself is slightly concave on the surface of the insulating layer. After chemical modification of the oxide, the two chips are pressed face to face, aligning each concave pad. Then slowly heat this laminated structure, allowing the copper to expand into the gap and fuse, thereby connecting the two chips.

1. Hybrid bonding starts from two wafers or a chip and a wafer facing each other. The mating surfaces are covered with an oxide insulating layer and slightly concave copper pads, which are connected to the chip's interconnect layer.

2. The wafers are pressed together to form an initial bonding between the oxides.3. Then, the stacked wafers are slowly heated so that the oxides firmly bond and the copper expands to form electrical connections.

a. To form a stronger bond, engineers need to flatten the last few nanometers of the oxide. Even slight bumps or warps can disrupt the dense connections.

b. The copper must be recessed from the oxide surface to just the right degree. Too much and the connection cannot be formed; too little and it will push the wafers apart. Researchers are studying how to control the copper to the level of individual atomic layers.

c. The initial connection between the wafers is a weak hydrogen bond. After annealing, the connection becomes a strong covalent bond. Researchers expect that using different types of surfaces, such as silicon carbide, there will be more positions to form chemical bonds, which will make the connection between the wafers more robust.

d. The final step of hybrid bonding may take several hours and requires high temperatures. Researchers hope to lower the temperature and shorten the process time.

e. Although the copper on the two wafers is pressed together to form an electrical connection, the grain boundaries of the metal usually do not pass through from one side to the other. Researchers are trying to form large single-crystal copper grains on the boundaries to improve electrical conductivity and stability.

Hybrid bonding can connect a single chip of one size to a wafer filled with larger chips, as well as bond two whole wafers of the same size together. Of course, the latter process is more mature than the former, partly because of its application in camera chips. For example, engineers at the European microelectronics research institution Imec have created some of the most dense wafer-to-wafer bonding ever, with a bonding distance (or pitch) of only 400 nanometers. However, Imec has only achieved a chip-to-wafer bonding pitch of 2 micrometers.

This is a significant improvement over today's advanced 3D chips in production (with a connection pitch of about 9 micrometers). And it is a much greater leap than the previous generation of technology: "microbumps" solder, with a pitch of tens of micrometers.

"After the device is available, aligning wafers with wafers is easier than aligning chips with wafers. Most microelectronic processes are targeted at whole wafers," said Jean-Charles Souriau, head of integration and packaging science at the French research institution CEA Leti. But chip-to-wafer (or chip-to-wafer) technology can shine in high-end processors, such as AMD's processors, which use new technology to assemble the computing cores and cache in their advanced CPUs and AI accelerators.To promote increasingly tight spacing under two circumstances, researchers focus on making surfaces flatter, binding the wafers more effectively together, and reducing the time and complexity of the entire process. Doing this well could revolutionize the way chips are designed.

WoW, Reducing Spacing

Recent wafer-on-wafer (WoW) research has achieved the tightest spacing — about 360 nanometers to 500 nanometers — which is a significant effort in one thing: flatness. To bind two wafers together with an accuracy of 100 nanometers, the entire wafer must be almost completely flat. If it is slightly curved or twisted, the whole section cannot be connected.

The planarization of the wafer requires a process called chemical mechanical planarization (CMP). It is essential for chip manufacturing, especially for producing interconnect layers above the transistors.

"CMP is the key parameter of the hybrid bonding that we must control," said Souriau. The results shown at ECTC demonstrated that CMP has been elevated to another level, not only making the entire wafer planarized but also reducing the roundness of the insulating layer between copper pads to the nanometer level to ensure better connections.

Other researchers are committed to ensuring that these flat parts can be bonded together firmly enough. They try using different surface materials, such as replacing silicon oxide with silicon nitride, and using different schemes to chemically activate the surface. Initially, when the wafer or chip is pressed together, they are fixed together by relatively weak hydrogen bonds, and the concern is whether they can stay in place during further processing steps. After the connection, the wafer and chip will slowly heat up, a process called annealing, aimed at forming stronger chemical bonds. How strong these bonds are — and even how to figure it out — is the subject of most of the research presented at ECTC.

The final bonding strength partly comes from the copper connection. The annealing step causes the copper to expand at the gap, forming a conductive bridge. Seung Ho Hahn of Samsung explained that controlling the size of the gap is key. If the expansion is too small, the copper will not fuse, and if it is too large, the wafer will be pushed away. This is a nanometer-level issue, and Hahn reported research on a new chemical process, hoping to achieve this by etching away a copper atomic layer at a time.

The quality of the connection is also important. The metal in the chip interconnect is not a single crystal; it is composed of many grains, which are oriented in different directions. Even after the copper expansion, the grain boundaries of the metal usually do not span from one side to the other. This spanning should reduce the resistance of the connection and improve its reliability. Researchers from Tohoku University in Japan reported a new metallurgical scheme that can ultimately generate large single-crystal copper across the boundary. "This is a huge change," said Associate Professor Takafumi Fukushima of Tohoku University. "We are now analyzing the reasons behind it."

Other experiments discussed at ECTC focused on simplifying the bonding process. Some people tried to reduce the annealing temperature required for bonding (usually around 300°C) to minimize the risk of damage to the chip caused by long-term heating. Researchers from Applied Materials introduced the progress of a method that can greatly reduce the time required for annealing — from several hours to just 5 minutes.

Excellent CoW EffectsImec uses plasma etching to cut chips and give them chamfered corners. This technique eliminates mechanical stress that could interfere with bonding.

Currently, Chip-on-Wafer (CoW) hybrid bonding is more useful for advanced CPU and GPU manufacturers: it allows chip manufacturers to stack chips of different sizes and test them before binding each chip to another, ensuring they won't cause problems. After all, a defective part dooms the fate of the entire expensive CPU.

However, CoW has all the difficulties of Wafer-on-Wafer (WoW), with fewer options to mitigate these difficulties. For example, CMP is designed to flatten wafers, not individual chips. Once the chips are cut from the source wafer and tested, fewer measures can be taken to improve their bonding readiness.

Nevertheless, Intel researchers reported CoW hybrid bonding with a pitch of 3 µm, and as mentioned above, a team at Imec successfully achieved a pitch of 2 µm, mainly by making the transferred dies very flat while they are still attached to the wafer and keeping them clean throughout the process.

Both teams used plasma etching to cut the chips, instead of the commonly used sawing method. Unlike sawing, plasma etching does not cause edge chipping, which can produce debris that may interfere with the connection. It also allows the Imec team to shape the chips, making chamfered corners to alleviate mechanical stress that could disrupt the connection.

Several researchers at ECTC said that CoW hybrid bonding is crucial for the future of high-bandwidth memory (HBM). HBM is a stack of DRAM dies on top of the control logic chip (currently 8-12 dies high). HBM is usually placed in the same package as high-end GPUs and is essential for handling the massive amounts of data required to run large language models like ChatGPT. Nowadays, HBM dies are stacked using microbump technology, so there are tiny solder balls surrounded by organic filler between each layer.

But as AI further increases memory requirements, DRAM manufacturers want to stack 20 layers or more in HBM chips. The volume occupied by microbumps means that these stacks will soon become too tall to fit properly into the GPU package. Hybrid bonding would reduce the height of HBM and make it easier to remove excess heat from the package, as the thermal resistance between layers would be smaller.

At ECTC, Samsung engineers demonstrated that hybrid bonding can produce a 16-layer HBM stack. Hyeonmin Lee, a senior engineer at Samsung, said, "I think it's possible to make stacks of more than 20 layers using this technology." Other new CoW technologies also help introduce hybrid bonding into high-bandwidth memory.

Souriau said that researchers at CEA Leti are exploring a technology called self-alignment. This will help ensure that good CoW connections can be achieved using only chemical processes. Certain parts of each surface will be made hydrophobic, while other parts will be made hydrophilic, causing the surfaces to automatically slide into place.At ECTC, researchers from Northeastern University and Yamaha Robotics reported on similar schemes, using the surface tension of water to align 5-µm pads on experimental DRAM chips with an accuracy better than 50-nm.

The upper limit of hybrid bonding

Researchers are almost certain to continue reducing the pitch of hybrid bonding connections. Han-Jong Chia, a pathfinding systems program manager at TSMC, said, "A 200 nm WoW pitch is not only possible but also ideal." TSMC plans to introduce a technology called backside power delivery within two years. Intel plans to achieve the same goal by the end of this year. This technology places the power transmission interconnects of the chip below the silicon surface instead of above it.

TSMC researchers have calculated that by excluding these power conduits, the top layer can be better connected to smaller hybrid bonding pads. Backside power delivery using 200 nm bonding pads will significantly reduce the capacitance of 3D connections, resulting in energy efficiency and signal speed measurements that are eight times better than those achieved with 400 nm bonding pads.

Chip-on-wafer hybrid bonding is more useful than wafer-on-wafer bonding because it can place a die of one size onto a wafer of a larger die. However, the achievable connection density is lower than that of wafer-on-wafer bonding.

Chia said that at some point in the future, if the bonding pitch is further reduced, "folding" circuit blocks may become practical. Some of the current long connections within the block may be able to take vertical shortcuts, thereby speeding up computation and reducing power consumption.

Moreover, hybrid bonding may not be limited to silicon. Souriau from CEA Leti said, "Today, there has been great progress in silicon-on-silicon wafers, but we are also exploring hybrid bonding between gallium nitride and silicon wafers, as well as glass wafers... everything is possible." They even proposed hybrid bonding for quantum computing chips, which involves aligning and bonding superconducting niobium instead of copper.